This invention relates to radios using frequency synthesizers. In particular, it is a circuit that enables a frequency synthesizer to achieve phase lock in a relatively short time.
A frequency synthesizer for use in a radio transmitter or receiver typically uses a controlled oscillator of some type to generate a signal at a frequency that is processed to provide a desired output. The output signal or some measure of the output signal is compared with a reference signal at a fixed frequency and the comparison is made part of a phase-locked loop to control the output frequency of the controlled oscillator. Several factors combined to place severe demands upon the design of such a circuit. First, it is desirable to make an unambiguous selection of a relatively large number of center frequencies, using only one reference frequency standard. Second, the frequency separation between adjacent channels used for land-mobile communication is normally fixed in a number of bands that vary in frequency by more than a decade. Finally, the trend to the use of higher and higher broadcast frequencies while maintaining the same channel separations places an increased requirement upon the precision of frequency control and the percentage change that must be made to select adjacent frequency channels.
The steps that are taken to solve the preceding problems often lead to another, that of speed of response. This becomes a problem because the objective of the typical phase-locked loop in a synthesizer is to develop a control voltage for a voltage-controlled oscillator (VCO). That control voltage maintains the VCO in phase-locked synchronism with a signal from a reference oscillator at a fixed frequency. Such a steady state is not difficult to maintain. However, when the system is first turned on or when it is desired to change the frequency of the VCO to select a different channel, the system must respond and recover phase lock in an acceptable length of time. That time is a function of the dynamics of the phase-locked loop. It is generally true that the output frequency of the VCO in a phase-locked loop is divided by a large number, of the order of thousands, to be compared with a reference signal to determine phase lock. The reference signal for comparison is typically no greater in frequency than the amount of separation between adjacent channels in the broadcast system and it may be an integral fraction of that separation. When a loop goes out of phase lock, the VCO is normally driven to its high or low extreme of frequency to provide a feedback signal that will recover synchronism. When this extreme is divided by the divisor of the divider in a phase-locked loop, the difference in frequency between the reference frequency and the divided extreme frequency may be as low as 0.1 Hz. This means that the time to change one-half cycle is more than 5 seconds. This is too long to wait for a synthesizer to settle at a new frequency.
The delay thus resulting is further compounded by the fact that it is normally necessary to filter the output of a phase detector that compares the reference frequency with the divided output of the VCO. The output of the phase detector is applied to a low-pass filter that has a cutoff below the reference frequency. The resulting loop dynamics in a typical system can result in a phase-lock time of the order of tens of seconds. Such a time delay is intolerable. A frequency synthesizer should achieve phase lock in a time that is substantially less than a second.